The presence of PS and PD varieties of all (or nearly all) SEE/AVX instructions has a historical context: Once upon a time, when Intel originally designed the first SSE instruction set, they thought that future chip architectures would have three domains: Integer, Single-Precision Floating Point (32-bit), Double-Precision Floating Point (64-bit)
Note: domains are segregated logic units within the CPU, and they matter because there's a small delay in transferring SSE/AVX register contents between them. Hence if a result from an instruction in the integer domain is used as an input to an instruction in a floating point domain, a 1 or 2 cycle delay may occur.
For this reason, Intel mirrored most logical bitwise and shuffle instructions three times: One for integers, one for SP-FP, and one for DP-FP. The operations performed by these mirrored instructions is identical -- including between integer and floating-point varieties.
At present time most x86 architectures have two domains: Integer and Floating Point. The FP domain handles both Single and Double-Precision (32/64 bit). Some architectures only have one domain for all SSE/AVX instructions. It is plausible that a third domain for double-precision could be added to some future architectures.