質問

I'm currently studying for an exam tomorrow and need some help understanding the following:


The following program is given:

ADDF R12, R13, R14

ADD R1,R8,R9

MUL R4,R2,R3

MUL R5,R6,R7

ADD R10,R5,R7

ADD R11,R2,R3

Find the potential conficts that can arise if the architecture has:

a) No pipeline

b) A Pipeline

c) Multiple pipelines


So for (b) I would say the instruction on line 5 is a Data Hazard because it fetches the value of R5 which is from the previous line given the result of a multiplication, so that instruction is not yet finished.

But what happens if an architecture doesn't have a pipeline? My best guess is that no hazards exist, but I'm not sure.

Also, what happens if it has 2 or more pipelines?

Cheers.

役に立ちましたか?

解決

You are correct to suggest that for a) there are no hazards as each instruction must complete before the next starts.

For b):

  • There is a "Read After Write" dependency between lines 4 and 5.
  • There are "Read After Read" dependencies between lines 4 and 5 and also between lines 2 and 6.

I suspect that the difference between parts b) and c) is that the question assumes you know ahead of time that the pipe-line has a well defined number of stages. For example we know that if the pipe-line has 3 stages then the RAR dependency between lines 2 and 6 is irrelevant.

In a system with multiple pipelines however the system could fetch say 4 instructions per cycle making dependencies that were formally too far apart now potential hazards.

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