VHDL中灵活/通用解码器的想法

Question

我想创建一个地址解码器，该解码器在更改选择器的位和解码输出信号的位数时可以使用，该解码器足够灵活。

因此，与其具有看起来像这样的静态（固定输入/输出大小）解码器：

entity Address_Decoder is
Generic
(
    C_INPUT_SIZE: integer := 2
);
Port
(
    input   : in  STD_LOGIC_VECTOR (C_INPUT_SIZE-1 downto 0);
    output  : out STD_LOGIC_VECTOR ((2**C_INPUT_SIZE)-1 downto 0);
    clk : in  STD_LOGIC;
    rst : in  STD_LOGIC
);
end Address_Decoder;

architecture Behavioral of Address_Decoder is

begin        
        process(clk)
            begin
               if rising_edge(clk) then 
                  if (rst = '1') then
                     output <= "0000";
                  else
                     case <input> is
                        when "00" => <output> <= "0001";
                        when "01" => <output> <= "0010";
                        when "10" => <output> <= "0100";
                        when "11" => <output> <= "1000";
                        when others => <output> <= "0000";
                     end case;
                  end if;
               end if;
            end process;

end Behavioral;

具有更灵活/一般的东西，看起来像这样：

    entity Address_Decoder is
    Generic
    (
        C_INPUT_SIZE: integer := 2
    );
    Port
    (
        input   : in  STD_LOGIC_VECTOR (C_INPUT_SIZE-1 downto 0);
        output  : out STD_LOGIC_VECTOR ((2**C_INPUT_SIZE)-1 downto 0);
        clk : in  STD_LOGIC;
        rst : in  STD_LOGIC
    );
    end Address_Decoder;

    architecture Behavioral of Address_Decoder is

    begin        

DECODE_PROC:
    process (clk)
    begin

        if(rising_edge(clk)) then
         if ( rst = '1') then
           output <= conv_std_logic_vector(0, output'length);
         else
           case (input) is
             for i in 0 to (2**C_INPUT_SIZE)-1 generate
             begin
                when (i = conv_integer(input)) => output <= conv_std_logic_vector((i*2), output'length);        
             end generate;
            when others => output <= conv_std_logic_vector(0, output'length);
           end case;
         end if;
        end if;
    end process;

    end Behavioral;

我知道此代码无效，并且“何时”测试用例必须是常数，并且我不能在类似的案例语句之间使用for-for-enerate，但是它表明了我所追求的是什么：一个实体足够聪明，可以满足我的需求。

我一直在尝试在没有太大成功的情况下找到一个优雅的解决方案，因此，我愿意接受任何建议。

预先感谢埃里克

Answer 1

显然，您希望输入是应设置的输出位的索引。

那样写。类似（假设来自numeric_std的类型）：

output <= (others => '0'); -- default
output(to_integer(input)) <= '1';

Answer 2

我总是发现，当您只循环每一位时，这种事情就更容易遵循，所以类似：

     if ( rst = '1') then
       output <= (others=>'0');
     else
       for i in 0 to (2**C_INPUT_SIZE)-1 generate
       begin
         if (i = conv_integer(input)) then
           output(i) <= '1';
         else
           output(i) <= '0';
         end if;
       end generate;
     end if;