What is the difference between == and === in Verilog?

Question

What is the difference between:

if (dataoutput[7:0] == 8'bx) begin

and

if (dataoutput[7:0] === 8'bx) begin 

After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)